The SpaceWire IP core complies with SpaceWire standard offering rich feature set. The Product Information Document provides core implementation overview. More information is provided in SpaceWire Low Level Design Document

The SpaceWire core;

• Supports routing switches with up to 32 links.
• Instantiates Altera or Xilinx (parameterized) libraries and can easily be converted other FPGA vendors or ASIC RTL.
• Supports LVDS drivers and receivers.
• Runs at frequency up to xxx MHz.
• Low resource utilisation. Uses xxx LE in Altera xxx device for node and xxx for xxx link routing switch.
• Supports flow control, wormhole routing, header deletion, virtual channels in network level
• Supports path addressing, logical addressing and regional and logical addressing, interval labeling, group adaptive routing for packets
• Supports broadcast and multicast packets
• Supports application level, exchange level and network level error handling and link error recovery Disconnect error, Parity error, Escape sequence error, Character sequence error, Credit error.
• A local node can be connected to a router to achieve router-node functionality without using external LVDS links.